Amitabh Yadav

Welcome to Amitabh's WebPage.

Nationality: Indian

I am a Research Fellow at CERN and an Affiliate at Lawrence Berkeley National Laboratory in California since October 2020. My current research revolves around Quantum Information, High-Performance Hw/Sw System Co-Design and HEP-ML for Fundamental Physics.

Prior to this, I was a post-MSc research associate at the Berkeley National Laboratory in the Physics Department under Dr. Heather Gray, where I worked on HEP.QPR Project. I obtained my M.Sc. in Computer Engineering from Delft University of Technology, the Netherlands in August 2019. My master thesis was supervised by Dr. Nader Khammassi and Prof. Dr. Koen Bertels at QCA Lab/QuTech on 'Micro-architecture Design for control of Spin-Qubit Quantum Processors', in collaboration with Intel Quantum Computing Lab, Hillsboro.

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• Quantum Computing (Hardware, Algorithms and FTQC)
• Hardware Engineering (in High Energy Physics, Quantum Computing etc.)
• Hw/Sw Co-design of Machine Learning applications in Fundamental Sciences, and
• IC/ASIC Design.

• Quantum Hough Transform for HEP Track-Reconstruction
  QHT.QPR is an under-development research with the HEP.QPR project at Berkeley Lab. Quantum Pattern Recognition (QPR) algorithms have the potential to provide orders of magnitude speed improvements and increased precision. The idea is developing QPR algorithms that could transform our ability to select and analyze challenging signatures of new physics, e.g. long-lived particles or high mass particles decaying to dense particle jets. Therefore expanding the HEP discovery potential for new particles and interactions.


• Shor's Algorithm on IBM Quantum Experience
  Running Shor's Algorithm using IBM Quantum Experience and Measuring the result by implementation on IBM's 5-Qubit Quantum Computer (Raven).

        ...continue to Git Hub

• CC-Spin: A Microarchitecture design for Control of Spin-QubitQuantum Accelerator (2020)
  In this overview paper, we analyze the control infrastructure requirements for Spin-Qubits, propose a Central-Control (CC-Spin) micro-architecture and a parameterized waveform generation methodology to integrate the physical Quantum chip with the OpenQL Quantum Compilation Tool-Chain. We have presented the quantum instruction execution flow via the CC-Spin micro-architecture, and the methodology of generating timing-precise I/Q and DC-waveform using Programmable Arbitrary Waveform Generators (AWG) hardware connected to the FPGA-based Micro-architecture.


• Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators (2019)
  This paper presents the definition and implementation of a quantum computer architecture to enable creating a full-fledged quantum computer.


• FE-I4 Firmware Development and Integration with FELIX for the Pixel Detector (2017)
  The read-out of the future ATLAS ITk detector is an engineering challenge for the routing of services and quality of the data. This paper describes the FPGA firmware development that integrates the GBT, Elink and Rx-Tx Cores for communication between the FE-I4 modules and the FELIX read-out system.


• Wireless Sensor Network Based Patient Health Monitoring and Tracking System (2017)
  This paper presents the structure of an embedded system that could monitor and keep a track of the patients’ position and health condition at all times.

        ...continue to Google Scholar

• Master Thesis 2019: Yadav, A., 2019. "CC-Spin: A Micro-architecture design for scalable control of Spin-Qubit Quantum Processor". TU Delft Education Repository.

Email: amitabhydv@gmail.com

place Office: 24-R-020
    CERN, Esplanade des Particules 1,
    1217 Meyrin, Geneva, Switzerland.